CATS: Cloaked Acoustic Transmission SchemeFall 2019-Fall 2020
Developed a modulation scheme that can encode digital data using inaudible signals hidden within music played over a speaker, by representing the data as individually-imperceptible phase offsets to the existing components of the audio (as an adaptation of the industry-standard OFDM technique). The final system, tested in simulation, supported roughly 150 bits per second of payload after applying error-correction algorithms -- Channel sensing and correction were explored in simulation but real-world testing was placed on hold due to the COVID-19 pandemic.
HackCooper 2019 ToolingSpring 2018-Fall 2019
Led a team of five students developing custom software to power the HackCooper 2019 hackathon, with features including streamlined sign-up, participant checkin, and judging. The backend runs on Google App Engine and presents a web interface for users and a protobuf-powered API for event staff use.
Created a minimal proof-of-concept for a node editor that generates valid GLSL code
Investigated deep learning approaches to audio source separation. Extended the work of Wave-U-Net, by investigating the use of penalization methods operating in the frequency domain, when combined with state-of-the-art time-domain network topologies. Tests included the successful separation of vocal and drum tracks from professionally-mastered songs.
Internet meme classifierSummer 2018
An application of TensorFlow and Python to the classification of visual Internet memes, including a retraining of the Inception v3 and MobileNet v2 image classifiers.
Autonomous boat control shieldCooper Union CoFPhE lab, Summer 2017
Designed a shield for Sparkfun's Arduino Fio v3 providing power, sensors, and motor control for a miniaturized autonomous boat in complex flows. Design includes multiple switching regulators, selectable motor voltage, lithium ion cell monitoring, an IMU, and two motor controllers and primarily uses readily-sourced SMD components.
Queens Plaza Interlocking SimulatorDigital Logic Design final project, December 2016
Designed and built a simulation of the signalling and train movement control systems found in the Queens Plaza Interlocking in the New York City subway system, using discrete CMOS logic for train and signal simulation and a Xilinx Spartan-3E FPGA for route generation.
Quadcopter for unmanned airdropEngineering Design and Problem Solving project, Fall 2016
Wired and configured the control systems for an unmanned quadcopter designed to drop parcels of food and beverages on a target. Our team was the only team to successfully complete all three airdrops required.
RailfishFacebook Global Hackathon entry, November 2016
Created the Java backend and routing engine for a project designed to crowdsource transit performance data from passengers of the New York City Subway in a privacy-conscious manner, in order to provide timely information on delays, crowding, and routing suggestions with greater accuracy and faster availability than current communication channels.
concert.fishHackCooper Hackathon project, September 2016
Wrote the backend, algorithmic demonstration, and machine learning code for a project that socially connects musicians and listeners in real time, and adaptively generates music based on real-time feedback using basic artificial intelligence. This project was selected as the winning project at this event.
FIRST Tech Challenge-compatible optical navigation sensor moduleSummer 2016
Designed an optical navigation module for competitive robotics utilizing an optical mouse sensor and a custom I2C to SPI bridge. Process included component sourcing, SMT layout using KiCAD, and Atmel microcontroller programming.
SafePlugModified Electrical Receptacle Cover for the Visually-Impaired, Fall 2015—Spring 2016
Designed, built, and tested product designs using Autodesk Inventor, 3D printing, CNC milling, and resin casting. We worked with the Northeast Association for the Blind at Albany to test prototypes with persons of varying degrees of vision impairment in a safe and controlled setting.
8-bit CPU on FPGASummer 2015
Designed a minimal 8-bit soft-core CPU on a Xilinx Spartan-3E FPGA using Verilog. A PDF writeup is available on Overleaf. With light optimization, the design was able to reliably reach over 100MHz on the Spartan-3E platform.
Numerical data analysis toolkit conversionSummer 2015
Converted a numerical data analysis and filtering toolkit from Visual Basic to PHP.